Non-Uniform HEVC Tile Partitioning Method for Asymmetric Multicores

This paper proposes a novel high efficiency video coding (HEVC) Tile partitioning method for the parallel processing by analyzing the computing ability of asymmetric multicores. The proposed method (i) analyzes the computing ability of asymmetric multicores and (ii) makes the regression model of computational complexity per video resolutions. Finally, the model (iii) determines the optimal HEVC Tile resolution for each core and partitions/allocates the Tiles to suitable cores. The proposed method minimizes the gap of decoding times between faster CPU cores and power-efficient cores (big/LITTLE cores). Experimental results with 4K UHD test sequences show average 20% improvement of decoding speedup on ARM asymmetric multicores system.